Electrical circuits and devices that execute instructions and process data have evolved becoming faster, larger and more complex. With the increased speed, size, and complexity of electrical circuits and data processors, data eye training has become more problematic, particularly in Double Data Rate (DDR) memory systems. As technologies for electrical circuits and processing devices have progressed, there has developed a greater need for efficiency, reliability and stability, particularly in the area of DDR memory data eye training.
Double Data Rate (DDR) memory devices use source synchronous clocking protocol to transfer the data between Memory and PHY. A DDR PHY or PHY is a DDR physical interface to DDR memory devices and drives address, command, and data pins of the memory device. The PHY acts as an interface between a memory controller and memory device to perform read/write data operations. The PHY can also perform various memory trainings to configure the PHY internal delay as well as some memory parameters to make sure memory read and write transactions are performed correctly. The double data rate architecture transfers two data words per clock cycle on the interface pins. In a typical DDR SDRAM, a bi-directional differential data strobe (DQS/DQS#) signal is sent externally, along with the data (DQ) signal. The DQS/DQS# signal is used to capture the DQ signal at the receiver. For Memory Write operation, PHY sends DQS/DQS# signal at the center of DQ, so write data can be captured properly at the memory. For Read operation, memory drives DQS/DQS# signal at the same time as DQ signal, and PHY delays the read DQS signal to place the DQS edges at the center of the DQ signal to effectuate proper capture the read data.
The DQ and DQS signal timing may be different at the receive end with respect to the transmit side due to mismatches between the DQ and DQS signal paths. The PHY performs required trainings to adjust the delay on DQS signal for both write and read operations to center align the DQS signal with respect to the DQ signal in order to have reliable data capture.
Current method to align DQS at the center of DQ is to perform a data eye training that detects extreme left and right points on data eye window for each Vref value. PHY compares the eye width for each Vref and selects the best Vref value that has the largest data eye width. The delay on DQS signal is selected to keep DQS edge in the middle of the data eye of the best Vref value.
This method provides best data eye width for a particular Vref value but does not guarantee required Vref margin. Vref margin refers to the amount of variation in Vref value with which reliable data transfers are guaranteed. Methods that try to detect the data eye width for a particular Vref and set the DQS delay in the middle work well but do not put the DQS signal in the broadest part of the eye.
For the foregoing reasons, there is a need for new methods and apparatuses for data eye training that overcome the problem associated with maximizing data eye width without taking into account of Vref margin in optimizing data eye training.